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ics9250-27 idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 frequency generator and integrated buffers for celeron & pii/iii tm 1 datasheet pin configuration recommended application: 810/810e and 815 type chipset. output features: ? 3 cpu (2.5v) (up to 133mhz achievable through i 2 c) 9 sdram (3.3v) (up to 133mhz achievable through i 2 c) 7 pci (3.3 v) @33.3mhz 2 ioapic (2.5v) @ 33.3 mhz 3 hublink clocks (3.3 v) @ 66.6 mhz 2 (3.3v) @ 48 mhz (non spread spectrum) 1 ref (3.3v) @ 14.318 mhz features: supports spread spectrum modulation, 0 to -0.5% down spread. i 2 c support for power management efficient power management scheme through pd# uses external 14.138 mhz crystal alternate frequency selections available through i 2 c control. 56-pin 300mil ssop * this input has a 50k ? pull-down to gnd. *fs2//ref0 vdd x1 x2 gnd gnd 3v66-0 3v66-1 3v66-2 vdd vdd pciclk_f pciclk0 gnd pciclk1 pciclk2 gnd pciclk3 pciclk4 pciclk5 vdd vdd gnd gnd 48mhz_0 48mhz_1 vdd fs0 gnd ioapic0 ioapic1 vddl cpuclk0 vddl0 cpuclk1 cpuclk2 gndl gnd sdram0 sdram1 vdd sdram2 sdram3 gnd sdram4 sdram5 vdd sdram6 sdram7 gnd sdram_f vdd pd# sclk s data fs1 ics9250-27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 block diagram ref0 cpu66/100/133 (2:0) vddl 3v66 (2:0) sdram (7:0) pciclk (5:0) ioapic (1:0) vddl sdram_f pciclk_f pll2 48mhz (1:0) x1 x2 xtal osc control logic config reg fs (2:0) pd# 2 3 3 8 6 2 /2 /2 /3 /2 pll1 spread spectrum sdata sclk functionality power groups avdd = pin 22 analog power for pll agnd = pin 23 analog ground vdd48 = pin 27 analog power for 48mhz pll gnd = pin 24 analog ground for 48mhz pll 2 s f1 s f0 s fn o i t c n u f x0 0 e t a t s i r t x0 1t s e t 010 z h m 6 6 = u p c e v i t c a z h m 0 0 1 = m a r d s 011 z h m 0 0 1 = u p c e v i t c a z h m 0 0 1 = m a r d s 110 z h m 3 3 1 = u p c e v i t c a z h m 3 3 1 = m a r d s 111 z h m 3 3 1 = u p c e v i t c a z h m 0 0 1 = m a r d s
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 2 pin description r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1 2 s fn i y t i l a n o i t c n u f t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . n i p t c e l e s n o i t c n u f 0 f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 31 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 42 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 3 2 , 7 1 , 4 1 , 6 , 5 , 7 4 , 1 4 , 5 3 , 4 2 6 5 , 8 4 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 7 , 8 , 9) 0 : 2 ( 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 , 1 2 , 1 1 , 0 1 , 2 , 8 3 , 3 3 , 7 2 , 2 2 4 4 d d vr w py l p p u s r e w o p v 3 . 3 2 1f _ k l c i c pt u ot u p t u o k c o l c i c p v 3 . 3 g n i n n u r e e r f , 6 1 , 8 1 , 9 1 , 0 2 3 1 , 5 1 ) 0 : 5 ( k l c i c pt u os t u p t u o k c o l c i c p v 3 . 3 5 20 _ z h m 8 4t u ob s u r o f s t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 6 21 _ z h m 8 4t u o o e d i v / s c i h p a r g r o f t u p t u o r e g n o r t s . t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 ) e t a r e g d e s n / v 1 m u m i n i m ( e c a f r e t n i 8 2 , 9 2) 0 : 1 ( s fn i t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . s n i p t c e l e s n o i t c n u f 1 e g a p n o e l b a t y t i l a n o i t c n u f o t r e f e r e s a e l p . y t i l a n o i t c n u f 0 3a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 1 3k l c sn ii f o n i p k c o l c 2 t n a r e l o t v 5 y r t i u c r i c c 2 3# d pn i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a o t n i t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a . s m 3 n a h t r e t a e r g e b , 0 4 , 9 3 , 7 3 , 6 3 6 4 , 5 4 , 3 4 , 2 4 ) 0 : 7 ( m a r d st u o f f o d e n r u t e b n a c s t u p t u o m a r d s l l a . z h m 0 0 1 g n i n n u r t u p t u o v 3 . 3 i h g u o r h t 2 c 4 3f _ m a r d st u o i h g u o r h t f f o d e n r u t e b t o n n a c , m a r d s z h m 0 0 1 g n i n n u r e e r f v 3 . 3 2 c 2 5 , 0 5 , 9 4 k l c u p c ) 0 : 2 ( t u o g n i d n e p e d z h m 3 3 1 r o z h m 0 0 1 , z h m 6 6 . t u p t u o k c o l c s u b t s o h v 5 . 2 . s n i p s f n o 3 5 , 1 5l d d vr w pc i p a o i & u p c r o f y l p p y u s r e w o p v 5 . 2 5 5 , 4 5) 0 : 1 ( c i p a o it u o. z h m 3 . 3 3 t a g n i n n u r s t u p t u o k c o l c v 5 . 2 the ics9250-27 is a single chip clock solution for 810/810e and 815 type chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces emi by 8db to 10 db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250- 27 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. general description
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 3 power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz maximum allowed current clock enable configuration # d pk l c u p cm a r d sc i p a o iz h m 6 6k l c i c p , f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on o 5 1 8 n o i t i d n o c n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 2 6 . 2 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p 0 = # n w d r w p ( a m 0 1a m 0 1 z h m 6 6 e v i t c a l l u f 0 1 0 = ] 0 : 2 [ s f a m 0 7a m 0 8 2 z h m 0 0 1 e v i t c a l l u f 1 1 0 = ] 0 : 2 [ s f a m 0 0 1a m 0 8 2 z h m 3 3 1 e v i t c a l l u f 1 1 1 = ] 0 : 2 [ s f
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 4 2 s f1 s f0 s fu p cm a r d s6 6 v 3i c pz h m 8 4f e rc i p a o i x00 e t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r t x0 1 2 / k l c t2 / k l c t3 / k l c t6 / k l c t2 / k l c tk l c t6 / k l c t 010 z h m 6 . 6 6z h m 0 0 1 6 . 6 6 z h m z h m 3 . 3 3z h m 8 4 8 1 3 . 4 1 z h m 3 . 3 3 z h m 011 z h m 0 0 1z h m 0 0 1 6 . 6 6 z h m z h m 3 . 3 3z h m 8 4 8 1 3 . 4 1 z h m 3 . 3 3 z h m 110 z h m 3 3 1z h m 3 3 1 6 . 6 6 z h m z h m 3 . 3 3z h m 8 4 8 1 3 . 4 1 z h m 3 . 3 3 z h m 111 z h m 3 3 1z h m 0 0 1 6 . 6 6 z h m z h m 3 . 3 3z h m 8 4 8 1 3 . 4 1 z h m 3 . 3 3 z h m truth table byte 0: control register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i bd i d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i bd i d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i bd i d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i bd i d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b m u r t c e p s d a e r p s ) f f o = 0 / n o = 1 ( 1) e v i t c a n i / e v i t c a ( 2 t i b6 21 z h m 8 41) e v i t c a n i / e v i t c a ( 1 t i b5 20 z h m 8 41) e v i t c a n i / e v i t c a ( 0 t i b9 42 k l c u p c1) e v i t c a n i / e v i t c a ( note: reserved id bits must be wirtten as "0". byte 1: control register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b6 37 m a r d s1) e v i t c a n i / e v i t c a ( 6 t i b7 36 m a r d s1) e v i t c a n i / e v i t c a ( 5 t i b9 35 m a r d s1) e v i t c a n i / e v i t c a ( 4 t i b0 44 m a r d s1) e v i t c a n i / e v i t c a ( 3 t i b2 43 m a r d s1) e v i t c a n i / e v i t c a ( 2 t i b3 42 m a r d s1) e v i t c a n i / e v i t c a ( 1 t i b5 41 m a r d s1) e v i t c a n i / e v i t c a ( 0 t i b6 40 m a r d s1) e v i t c a n i / e v i t c a ( notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 5 byte 3: ics reserved functionality and frequency select register (default as noted in pwd) note 1: for system operation, the bsel lines of the cpu will program fs0, fs2 for the appropriate cpu speed, always with sdram = 100mhz. after bios verifies the sdram is pc133 speed, then bit 0 can be written from the default 0 to 1 to change the sdram output frequency from 100mhz to 133mhz. this will only change if the cpu is at the 133mhz fsb speed as shown in this table. the cpu, 3v66, pci, and ioapic clocks will be glitch free during this transition, and only sdram will change. note 2: "ics reserved bits" must be writtern as "o". note3: undefined bits can be written either as "1 or 0" t i bn o i t p i t c s e dd w p 7 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 6 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 5 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 4 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 3 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 2 t i b) 3 e t o n ( t i b d e n i f e d n u x 1 t i b) 3 e t o n ( t i b d e n i f e d n u x 0 t i b 0 t i b0 s f1 s f k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p z h m c i p a o i z h m 0 1 e t o n 000 6 6 . 6 60 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 010 0 . 0 0 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 001 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3 011 2 3 . 3 3 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 100 6 6 . 6 60 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 110 0 . 0 0 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 10 1 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3 111 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3 byte 2: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default 3. undefined bit can be wirtten with either a "1" or "0". t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b9 ) p g a ( 2 - 6 6 v 31) e v i t c a n i / e v i t c a ( 6 t i b0 25 k l c i c p1) e v i t c a n i / e v i t c a ( 5 t i b9 14 k l c i c p1) e v i t c a n i / e v i t c a ( 4 t i b8 13 k l c i c p1) e v i t c a n i / e v i t c a ( 3 t i b6 12 k l c i c p1) e v i t c a n i / e v i t c a ( 2 t i b5 11 k l c i c p1) e v i t c a n i / e v i t c a ( 1 t i b3 10 k l c i c p1) e v i t c a n i / e v i t c a ( 0 t i b- t i b d e n i f e d n ux) e v i t c a n i / e v i t c a (
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 6 byte 4: reserved register (1 = enable, 0 = disable) byte 5: reserved register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 2 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 1 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 2 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 1 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default group timing relationship table 1 p u o r gz h m 6 6 u p c z h m 0 0 1 m a r d s z h m 0 0 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 3 3 1 m a r d s t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t m a r d s o t u p cs n 5 . 2s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 6 6 v 3 o t u p cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 - 5 . 1a / ns n 5 . 3 - 5 . 1a / ns n 5 . 3 - 5 . 1a / ns n 5 . 3 - 5 . 1a / n i c p o t c i p a o is n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1 t o d & b s uh c n y s aa / nh c n y s aa / nh c n y s aa / nh c n y s aa / n
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 7 absolute maximum ratings core supply voltage 4.6 v i/o supply voltage 3.6v logic inputs gnd ?0.5 v to v dd +0.5 v ambient operating temperature 0c to +70c storage temperature ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a i il1 v in = 0 v; inputs with no pull-up resistors -5 2 i il2 v in = 0 v; inputs with pull-up resistors -200 -100 c l = 0 pf; select @ 66 mhz 97 115 c l = 0 pf; select @ 100 mhz 91 110 c l = 0 pf; select @ 133 mhz 100 165 c l = max loads; select @ 66 mhz 295 330 c l = max loads; select @ 100 mhz 280 320 c l = max loads; select @ 133 mhz 300 395 c l = 0 pf; select @ 66 mhz 16 19 c l = 0 pf; select @ 100 mhz 25 35 c l = 0 pf; select @ 133 mhz 26 40 c l = max loads; select @ 66 mhz 19 30 c l = max loads; select @ 100 mhz 34 50 c l = max loads; select @ 133 mhz 40 70 i dd3.3pd c l = max loads 220 400 i dd.25pd input address vdd or gnd <1 10 input frequency f i v dd = 3.3 v 12 14.318 16 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 5 ms settling time 1 t s from 1st crossing to 1% target frequency 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 5 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. delay 1 ma ma input capacitance 1 i dd2.5op a powerdown current operating supply current input low current a ma ma i dd3.3op
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 8 electrical charact eristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 22 45 ? output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 23 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns v t = 1.25 v, 66, 100 mhz 45 50 55 v t = 1.25 v, 133 mhz 45 53 55 skew window 1 t sk2b v t = 1.25 v 118 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 148 250 ps 1 guaranteed by design, not 100% tested in production. % d t2b duty cycle 1 ma ma output high current output low current i oh2b i ol2b electrical charact eristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 17 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 18 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -108 v oh @ max = 3.135 v -9 -33 v ol @ min = 1.95 v 30 95 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.2 1.8 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.3 1.8 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew window 1 t sk1 v t = 1.5 v 82 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 123 500 ps 1 guaranteed by design, not 100% tested in production. output high current output low current ma ma i oh1 i ol1
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 9 electrical characteristics - ioapic t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 21.5 30 ? output impedance r dsn4b 1 v o = v dd *(0.5) 9 23 30 ? output high voltage v oh4b i oh = -1 ma 2 v output low voltage v ol4b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 50 55 % jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 123 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh4b ma output low current i ol4b ma electrical charact eristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 14 24 ? output impedance r dsn3 1 v o = v dd *(0.5) 10 18 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v v oh @ min = 2.0 v -54 -92 v oh @ max = 3.135 v -16 -46 v ol @ min = 1.0 v 54 68 v ol @ max = 0.4 v 29 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.5 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 52 55 % skew window 1 t sk3 v t = 1.5 v 164 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh3 i ol3 250 jitter, cycle-to-cycle 1 t jcyc-cyc3 ps v t = 1.5 v, 66, 100 mhz 180
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 10 electrical charact eristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 14 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 18 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -106 v oh @ max = 3.135 v -14 -33 v ol @ min = 1.95 v 30 94 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.3 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.4 2 ns duty cycle 1 d t1 v t = 1.5 v 45 52 55 % skew window 1 t sk1 v t = 1.5 v 304 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 170 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma electrical characteristics - ref, 48mhz_0 (pin 25) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 32.6 60 ? output impedance r dsn5 1 v o = v dd *(0.5) 20 31 60 ? output high voltage v oh15 i oh = -1 ma 2.4 v output low voltage v ol5 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -29 -54 v oh @ max = 3.135 v -11 -23 v ol @ min = 1.95 v 29 54 v ol @ max = 0.4 v 16 27 rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 1.4 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.4 1.7 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % jitter, cycle-to-cycle 1 t j c y c-c y c5 v t = 1.5 v, fixed clocks 215 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, ref clocks 930 1000 ps 1 guaranteed by design, not 100% tested in production. output high current i oh5 ma output low current i ol5 ma
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 11 electrical characteristi cs - 48mhz_1 (pin 26) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-15 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 16.7 24 ? output impedance r dsn3 1 v o = v dd *(0.5) 10 18.4 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.55 v v oh @ min = 2.0 v -54 -82 v oh @ max = 3.135 v -20 -46 v ol @ min = 1.0 v 54 95 v ol @ max = 0.4 v 28 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1.1 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 51 55 % skew t sk3 v t = 1.5 v 116 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc3b v t = 1.5 v 196 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh3 ma output low current i ol3 ma
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 12 group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.3v 66mhz pci 33mhz ioapic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 13 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) st art bit address d2 (h ) a ck dummy command code a ck dumm y byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to write: controller (host) ics (slave/receiver) st art bit address d3 (h ) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read:
idt tm frequency generator and integrated buffers for celeron & pii/iii tm 0395f?01/25/10 ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 14 ordering information 9250 y f-27lf-t designation for tape and reel packaging rohs compliant (optional) pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) example: xxxx y f - ppp lf - t min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 variations min max min max 56 18.31 18.55 .720 .730 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d (inch) symbol see variations see variations
ics9250-27 frequency generator and integrated buffers for celeron & pii/iii tm 15 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2009 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision histor y rev. issue date description pa g e # c 8/17/2005 added lf ordering information 14 d 10/25/2005 removed "contact ics for an i 2 c programming application" note reference. 13 e 9/11/2008 corrected typo on pin# 28/29 pin description 2 f 1/25/2010 updated document template

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